Applications of OPAMP

Physical design

Below are the steps in the physical design 1) Pin placement and floorplan 2) placement of standard cells 3) clock tree synthesis 4) routing 5) Signoff Floorplan and pin placement Inputs for floorplan 1) netlist 2) dbs or libs 3) tech file 4) sdc constraints 5) lef file Sanity checks for floorplan 1) check library it will check consistency between timing libs and physical libraries 2) check timing it will check if constraints are applied properly or not like clock is available or not , input delay or output delay is applied or not, timing exceptions like false path, multicycle is applied or not also half cycle path or false path . 3 check netlist check if there is undriven pin or not , Unloaded output ,multi driven pin or not and combinational loop is there or not After sanity check we move to floorplan guide lines 1) there should be macro to macro spacing based on the channel spacing formula...

OPAMP Designing

Two stage compensated CMOS Op-Amp and its applications (Voltage regulator and Comparator) ABSTRACT This paper describes the designing and simulation of various parameters of-Two stage compensated Op-Amp using with high gain, high PSRR, high CMRR and low power. Circuit is applied to operate at lower supply voltage (5V). Achievement of high gain around 90db, 60 degree phase margin for stable closed loop operations were the goal of primary concern. Simulation had been carried out using Pspice Orcad simulator . 1.Introduction Op-Amp is among today’s most widely used circuit blocks. They can be used to realize summers, integrators, attenuators, comparators, differentiators etc. An Op-amp is a high-gain differential input amplifier. Various characteristics of Op-Amp include high CMRR, high PSRR and a high Slew Rate. Commonly used configuration for CMOS Op-Amp is the two stage amplifier. A differential front end which converts a differential voltage ...

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