Physical design

 Below are the steps in the physical design 

1) Pin placement and floorplan

2) placement of standard cells 

3) clock tree synthesis 

4) routing 

5)  Signoff

Floorplan and pin placement 

Inputs for floorplan 1) netlist 2) dbs or libs 3) tech file 

4) sdc constraints 5) lef file  

Sanity checks for floorplan 

1) check library it will check consistency between timing libs and physical libraries 

2) check timing it will check if constraints are applied properly or not like clock is available or not , input delay or output delay is applied  or not, timing exceptions like false path, multicycle is applied or not also half cycle path or false path . 

3 check netlist check if there is undriven  pin or not , Unloaded output ,multi driven pin or not and combinational loop is there or not 

After sanity check we move to floorplan guide lines 

1) there should be macro to macro spacing based on the channel spacing formula : number of pins * pitch /2* number of layers 

2) macros should be placed based on there hierarchy I.e that are talking to each other should placed nearer to  eachothers 

3) side of macros that are not talking to each others should be abutted together .

4) side of macros that are talking to each other should be oriented towards each others .

5) there should be space between macros for VDD and VSS

6) No notches should be there if present place the placement blockage near the notch

7) macros should be placed based on fly lines 

In floorplan we need to have aspect ratio W/H 

ar = w/ h 

W = ar* h 

Area = h * w 

Area = h * ar * h 

h square = area / ar 

h = square root area /ar 

W= ar * h

Area = (Gate count + extra gate count after cts and ecos / Gate density + area of macros + area by i/o pads ) / utilisation 

After initialisation of floorplan, macro and pin /port placement we move to power planning . 

We need to create the ring command for same is addring  

After that we create the stripes command for same is  add stripe . Then we need to give power to the macros we use the command sroute , 

Blockages should be added there are 3 types of blockages 

1) hard blockages it wont allow any buffer or standard cell placement .

2 ) soft blockages only during optimisation buffer or inverters are allowed , 

3) partial blockages only percentage of cells are allowed 

After power planning we place the end cap cells and tap cells . 

Checks after floorplan 

1) macros are placed and fixed 

2) pin/ port are placed and legalised 

3) blockages are placed properly 

4) macros are legalised 

5) notches should be avoided 

6) tap cells are placed at proper distance 

7) checkfplan 

8) verifydrc 

9) check pin assignment