Library exchange format(LEF) and Design exchange format (DEF)

LEF /DEF

Library exchange format has information about standard cells and technology .

LEF can be divided into two parts
a)CELL LEF
b)Technology LEF
Note Technology LEF is read first and after that CELL LEF is read .
Cell lef has following information .

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[VIA statement] ...
[SITE statement]
[MACRO statement
[PIN statement] ...
[OBS statement ...] ] ...
[BEGINEXT statement] ...
[END LIBRARY]

[VERSION statement]

Version information specifies that what is the version of LEF /DEF format.

[BUSBITCHARS "delimiterPair" ;]
Specifies the pair of characters used to specify bus bits when LEF names are mapped to or
from other databases. The characters must be enclosed in double quotation marks. For
example:
BUSBITCHARS "[]" ;

Busbitchars means that all the commands will be specified between []


Divider Character
[DIVIDERCHAR "character" ;]

this information used for hierarchical design it is specified between different levels in hierarchy
eg if there is a block A (top level )B,C (sub blocks ) we can refer them as A/B and A/C .


[VIA statement] ...
VIA layers are defined as layer type cut
metal layers are defined as layer type routing
You must define layers in process order from bottom to top. For example:
poly masterslice
cut01 cut
metal1 routing
cut12 cut
metal2 routing
cut23 cut
metal3 routing

SITE siteName [sitePattern]
Specifies the site associated with the macro. Normal rowbased
standard cells only have a single SITE siteName
statement, without a sitePattern. The sitePattern
syntax indicates that the cell is a gate-array cell, rather than a
row-based standard cell. Gate-array standard cells can have
multiple SITE statements, each with a sitePattern.

MACRO myTest
CLASS CORE ;
SIZE 10.0 BY 14.0 ; #Uses 2 F and 1 L site, is F + L wide, and double height
SYMMETRY X ; #Can flip about the X axis
SITE Fsite 0 0 N ; #The lower left Fsite at 0,0
SITE Fsite 0 7.0 FS ; #The flipped south Fsite above the first Fsite at 0,7
SITE Lsite 4.0 0 N ; #The Lsite to the right of the first Fsite at 4,0
...
PIN ... ;
END myTest

[MACRO statement]
Tells about the macros in the design .

[PIN statement]
Defines pins for the macro.

[OBS statement ...]

Defines a set of obstructions (also called blockages) on the macro.


A technology LEF file contains all of the LEF technology information for a design, such as
placement and routing design rules, and process information for layers. A technology LEF file
can include any of the following LEF statements:
[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[UNITS statement]
[MANUFACTURINGGRID statement]
[USEMINSPACING statement]
[CLEARANCEMEASURE statement ;]
[PROPERTYDEFINITIONS statement]
[LAYER (Nonrouting) statement
| LAYER (Routing) statement] ...
[MAXVIASTACK statement]
[VIA statement] ...
[VIARULE statement] ...
[VIARULE GENERATE statement] ...
[NONDEFAULTRULE statement] ...
[SITE statement] ...
[BEGINEXT statement] ...
[END LIBRARY]

[VERSION statement]
same as cell LEF

[BUSBITCHARS statement]
same as cell LEF

[DIVIDERCHAR statement]
same as cell LEF

[UNITS statement]
specifies units defined in LEF and default units is um

[MANUFACTURINGGRID value ;]
Defines the manufacturing grid for the design. The manufacturing grid is used for geometry
alignment. When specified, shapes and cells are placed in locations that snap to the
manufacturing grid.


[USEMINSPACING OBS { ON | OFF } ;]
Defines how minimum spacing is calculated for obstruction (blockage) geometries.


Layer and Via information is also specified .




DEF(Design exchange format)

A Design Exchange Format (DEF) file contains the design-specific information of a circuit and is a representation of the design at any point during the layout process.

DEF conveys logical design data to, and physical design data from, place-and-route tools.

Logical design data can include internal connectivity (represented by a netlist), grouping

information, and physical constraints. Physical data includes placement locations and

orientations, routing geometry data, and logical design changes for backannotation. Place and route tools also can read physical design data, for example, to perform ECO changes.