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OPAMP Designing

Two stage compensated CMOS Op-Amp and its applications (Voltage regulator and Comparator)
ABSTRACT
This paper describes the designing and simulation of various parameters of-Two stage compensated Op-Amp using with high gain, high PSRR, high CMRR and low power. Circuit is applied to operate at lower supply voltage (5V). Achievement of high gain around 90db, 60 degree phase margin for stable closed loop operations were the goal of primary concern.  Simulation had been carried out using Pspice Orcad simulator.  

1.Introduction 

Op-Amp is among today’s most widely used circuit blocks. They can be used to realize summers, integrators, attenuators, comparators, differentiators etc. An Op-amp is a high-gain differential input amplifier. Various characteristics of Op-Amp include high CMRR, high PSRR and a high Slew Rate. Commonly used configuration for CMOS Op-Amp is the two stage amplifier. A differential front end which converts a differential voltage into a current and a common source output stage that converts the signal current into an output voltage.



Fig 1.TWO stage OPAMP Diagram



2. PSPICE
SPICE stands for Simulation Program Integrated Circuit Emphasis.  In PSPICE, P stands for Personal edition. Various program for DC, AC and Transient analysis can be written using SPICE. SPICE program can be simulated using Pspice Orcad simulator.



 3. DESIGN PROCEDURE
1. Choose the smallest device length which will keep the channel modulation parameter constant   and give matching for current mirror.
2. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60 degree phase  margin we use the following relationship. This assumes that
      Z>=10GB.
      CC > 0.22CL      
3. Determine the minimum value for the “tail current” (I5) from the larger of the two values.
       I5=SR*CC                                                         
4. Design for S3 from the maximum input voltage specification                                                      
S3=(2*I5)/K3*[VDD-VIN(max)-VTO3(MAX)+ VT1(MIN)]2                                                       
5. Verify that the pole of M3 due to Cgs3 and Cgs4 will not be dominant by assuming p3 to be greater than10GB.    
6. Design for S1 and S2                                            
        gm1 = (GB*Cc)
         S1 = S2 = gm2 / (k2 * I5)                                                                                                                                                                 
7. Design for S5 and S8            
        S5=S8=(2*I5)/(K5*Vds5(sat)2)                                                                                                                                                                                                                                                                                                                                                          
 8. Find S6 and I6, letting second pole equal to 2.2 GB.    
         S6=(S4*gm6)/gm4                                                                                                                                           
 9. Knowing gm6, s6 allows us to find I6  
        I6 = gm62 / (2 * k6 * S6)                                                                                               
10. Design S7 to achieve desired current ratio between I5 and I6.   
        S7 = (S5 * I6) / I5                                                                 
11. Simulate the circuit to check for all specifications are met.
4. RESULT
W and L values calculated for various MOSFETs used in the circuit.
MOSFET
W(µm)/l(um)

M1
3u

M2
3u

M3
15u

M4
15u

M5
4.5u

M6
94u

M7
14u

M8
4.5u


Following table compares the required specifications with the obtained values.
DESIGN PARAMETER
SPECIFICATION
OBTAINED
GAIN,AV
80db
90db
CL
10pf
10pf
VDD
2.5V
2.5V
VSS
-2.5V
-2.5V
UGB
5MHz
5MHz
SLEW RATE
10V/µs
5V/µs
CMRR
>80db
210db
PSRR
>80db
90db
ICMR
-2.5V to +2.5V
-1.7V to 2.4V

5. SIMULATIONS
Open loop simulation of the Op-Amp is shown in fig.2


Fig 2 Open loop gain 

Frequency response of  the Op-amp is shown in fig.3. using frequency response Unity Gain Bandwidth (UGB), Gain, Phase margin and Gain margin can be determined, which are the major AC parameters of the Op-Amp.  

Fig3 Frequency response 

Fig.4 shows the simulation of Common Mode Rejection Ratio (CMRR) of Op-Amp. Value of CMRR estimated to be                                                                                                                     210db. Circuit diagram for simulation of CMRR

                                            \

Fig 4 Simulation of CMRR

Simulation result of Input Common Mode Range ICMR is shown in fig.5. ICMR estimated to be -1.8V to 2.4V. Circuit diagram for simulation of ICMR..


Fig 5 Simulation of ICMR


Fig.6.shows the simulation of Power Supply Rejection ratio (PSRR).PSRR specify the change in input offset voltage with change in supply voltage. Circuit diagram for simulation of PSRR



                                                                                                 FIG 6 Simulation PSRR

.     
       
Slew Rate can be determined using the transient analysis simulation as shown in fig.7. Circuit diagram for Slew Rate simulation is shown in fig. 


Fig 7 Slew Rate

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