Below are the steps in the physical design 1) Pin placement and floorplan 2) placement of standard cells 3) clock tree synthesis 4) routing 5) Signoff Floorplan and pin placement Inputs for floorplan 1) netlist 2) dbs or libs 3) tech file 4) sdc constraints 5) lef file Sanity checks for floorplan 1) check library it will check consistency between timing libs and physical libraries 2) check timing it will check if constraints are applied properly or not like clock is available or not , input delay or output delay is applied or not, timing exceptions like false path, multicycle is applied or not also half cycle path or false path . 3 check netlist check if there is undriven pin or not , Unloaded output ,multi driven pin or not and combinational loop is there or not After sanity check we move to floorplan guide lines 1) there should be macro to macro spacing based on the channel spacing formula : number of pins * pitch /2* number of layers 2) macros should be placed base
LEF /DEF Library exchange format has information about standard cells and technology . LEF can be divided into two parts a)CELL LEF b)Technology LEF Note Technology LEF is read first and after that CELL LEF is read . Cell lef has following information . [VERSION statement] [BUSBITCHARS statement] [DIVIDERCHAR statement] [VIA statement] ... [SITE statement] [MACRO statement [PIN statement] ... [OBS statement ...] ] ... [BEGINEXT statement] ... [END LIBRARY] [VERSION statement] Version information specifies that what is the version of LEF /DEF format. [BUSBITCHARS "delimiterPair" ;] Specifies the pair of characters used to specify bus bits when LEF names are mapped to or from other databases. The characters must be enclosed in double quotation marks. For example: BUSBITCHARS "[]" ; Busbitchars means that all the commands will be specified between [] Divider Character [DIVIDERCHAR "character" ;] this information used for