Below are the steps in the physical design 1) Pin placement and floorplan 2) placement of standard cells 3) clock tree synthesis 4) routing 5) Signoff Floorplan and pin placement Inputs for floorplan 1) netlist 2) dbs or libs 3) tech file 4) sdc constraints 5) lef file Sanity checks for floorplan 1) check library it will check consistency between timing libs and physical libraries 2) check timing it will check if constraints are applied properly or not like clock is available or not , input delay or output delay is applied or not, timing exceptions like false path, multicycle is applied or not also half cycle path or false path . 3 check netlist check if there is undriven pin or not , Unloaded output ,multi driven pin or not and combinational loop is there or not After sanity check we move to floorplan guide lines 1) there should be macro to macro spacing based on the channel spacing formula : number of pins * pitch /2* number of layers 2) macros should be placed base